The present invention relates to a method for selecting a spare column and a circuit thereof for reading and storing data from and into a memory cell using MOS transistors.
In a circuit constructed with MOS transistors for reading and storing data from and into a memory cell, a normal bit line and a spare bit line exist. If there is something wrong in the normal bit line, it is widely known that data is read and written from and into a memory cell with the spare bit line.
In the prior art of selecting a spare column with a spare bit line, however, a clock signal which is produced by cutting a fuse for the spare column enables a spare column decoder after disabling a normal column decoder. Such method causes defects as are described below.
First, since the spare column is to be selected after disabling the normal column decoder, some delay time occurs which decreases speed in case of using the spare column. When the spare column and normal column are concurrently selected without this time delay, for a read cycle, a direct current path occurs through an input/output line between a sense amplifier of the spare bit line and that of the normal bit line during the read cycle; and for a write cycle, since data is concurrently written through the spare bit line and normal bit line, loading effect of bit line is doubled.
Second, when the spare column is selected, since the clock signal for selecting the spare column is applied to the normal decoder to disable the normal column decoder, the construction of logic schemetic becomes complicated.